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The individual flash memory cells exhibit internal characteristics similar to those of the corresponding gates. Whereas EPROMs had to be completely erased before being rewritten, NAND-type flash memory may be written and read in blocks (or pages) which are generally much smaller than the entire device. NOR-type flash allows a single machine word (byte) to be written to an erased location or read independently. The NAND type operates primarily in memory cards, USB flash drives, solid-state drives (those produced in 2009 or later), and similar products, for general storage and transfer of data. NAND or NOR flash memory is also often used to store configuration data in numerous digital products, a task previously made possible by EEPROM or battery-powered static RAM. One key disadvantage of flash memory is that it can only endure a relatively small number of write cycles in a specific block.
Example applications of both types of flash memory include personal computers, PDAs, digital audio players, digital cameras, mobile phones, synthesizers, video games, scientific instrumentation, industrial robotics, and medical electronics. In addition to being non-volatile, flash memory offers fast read access times, although not as fast as static RAM or ROM.  Its mechanical shock resistance helps explain its popularity over hard disks in portable devices, as does its high durability, ability to withstand high pressure, temperature and immersion in water, etc. Although flash memory is technically a type of EEPROM, the term EEPROM is generally used to refer specifically to non-flash EEPROM which is erasable in small blocks, typically bytes.
[ citation needed] Because erase cycles are slow, the large block sizes used in flash memory erasing give it a significant speed advantage over non-flash EEPROM when writing large amounts of data. As of 2013[update],[ needs update?] flash memory costs much less than byte-programmable EEPROM and had become the dominant memory type wherever a system required a significant amount of non-volatile solid-state storage. Contents1 History2 Principles of operation2.1 Floating-gate transistor2.1.1 Internal charge pumps2.2 NOR flash2.2.1 Programming2.2.2 Erasing2.3 NAND flash2.3.1 Writing and erasing2.4 Vertical NAND2.4.1 Structure2.4.2 Construction2.4.3 Performance3 Limitations3.1 Block erasure3.2 Memory wear3.3 Read disturb3.4 X-ray effects4 Low-level access4.1 NOR memories4.2 NAND memories4.3 Standardization5 Distinction between NOR and NAND flash5.1 Write endurance6 Flash file systems7 Capacity8 Transfer rates9 Applications9.1 Serial flash9.1.1 Firmware storage9.2 Flash memory as a replacement for hard drives9.3 Flash memory as RAM9.4 Archival or long-term storage10 Industry11 Flash scalability12 See also13 References14 External links History [ edit ]This section needs additional citations for verification. Please help improve this article by adding citations to reliable sources.
Unsourced material may be challenged and removed. (July 2010) ( Learn how and when to remove this template message)Flash memory (both NOR and NAND types) was invented by Fujio Masuoka while working for Toshiba circa 1980.  According to Toshiba, the name flash was suggested by Masuokas colleague, Shji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera.
 Masuoka and colleagues presented the invention at the IEEE 1984 International Electron Devices Meeting (IEDM) held in San Francisco. Intel Corporation saw the massive potential of the invention and introduced the first commercial NOR type flash chip in 1988.  NOR-based flash has long erase and write times, but provides full address and data buses, allowing random access to any memory location. This makes it a suitable replacement for older read-only memory (ROM) chips, which are used to store program code that rarely needs to be updated, such as a computers BIOS or the firmware of set-top boxes.
Its endurance may be from as little as 100 erase cycles for an on-chip flash memory, to a more typical 10,000 or 100,000 erase cycles, up to 1,000,000 erase cycles.  NOR-based flash was the basis of early flash-based removable media; CompactFlash was originally based on it, though later cards moved to less expensive NAND flash. NAND flash has reduced erase and write times, and requires less chip area per cell, thus allowing greater storage density and lower cost per bit than NOR flash; it also has up to 10 times the endurance of NOR flash. However, the I/O interface of NAND flash does not provide a random-access external address bus. Rather, data must be read on a block-wise basis, with typical block sizes of hundreds to thousands of bits.
This makes NAND flash unsuitable as a drop-in replacement for program ROM, since most microprocessors and microcontrollers require byte-level random access. In this regard, NAND flash is similar to other secondary data storage devices, such as hard disks and optical media, and is thus, highly suitable for use in mass-storage devices, such as memory cards. The first NAND-based removable media format was SmartMedia in 1995, and many others have followed, including:MultiMediaCardSecure DigitalMemory Stick, and xD-Picture Card. A new generation of memory card formats, including RS-MMC, miniSD and microSD, feature extremely small form factors.
For example, the microSD card has an area of just over 1.5cm2, with a thickness of less than 1mm. microSD capacities range from 64 MB to 256 GB, as of May 2016. A flash memory cell. Principles of operation [ edit ]Flash memory stores information in an array of memory cells made from floating-gate transistors. In single-level cell (SLC) devices, each cell stores only one bit of information. In multi-level cell (MLC) devices, including triple-level cell (TLC) devices, can store more than one bit per cell.
The floating gate may be conductive (typically polysilicon in most kinds of flash memory) or non-conductive (as in SONOS flash memory).  Floating-gate transistor [ edit ]Main article: Floating-gate MOSFETIn flash memory, each memory cell resembles a standard MOSFET, except that the transistor has two gates instead of one. On top is the control gate (CG), as in other MOS transistors, but below this there is a floating gate (FG) insulated all around by an oxide layer.
The FG is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, electrons placed on it are trapped until they are removed by another application of electric field (e.g. Applied voltage or UV as in EPROM). Counter-intuitively, placing electrons on the FG sets the transistor to the logical 0 state.
Once the FG is charged, the electrons in it screen (partially cancel) the electric field from the CG, thus, increasing the threshold voltage (V T1) of the cell. This means that now a higher voltage(V T2) must be applied to the CG to make the channel conductive. In order to read a value from the transistor, an intermediate voltage between the threshold voltages (V T1 & V T2) is applied to the CG. If the channel conducts at this intermediate voltage, the FG must be uncharged (if it were charged, we would not get conduction because the intermediate voltage is less than V T2), and hence, a logical 1 is stored in the gate. If the channel does not conduct at the intermediate voltage, it indicates that the FG is charged, and hence, a logical 0 is stored in the gate. The presence of a logical 0 or 1 is sensed by determining whether there is current flowing through the transistor when the intermediate voltage is asserted on the CG.
In a multi-level cell device, which stores more than one bit per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG. Internal charge pumps [ edit ]Despite the need for high programming and erasing voltages, virtually all flash chips today require only a single supply voltage, and produce the high voltages using on-chip charge pumps. Over half the energy used by a 1.8 V NAND flash chip is lost in the charge pump itself. Since boost converters are inherently more efficient than charge pumps, researchers developing low-power SSDs have proposed returning to the dual Vcc/Vpp supply voltages used on all the early flash chips, driving the high Vpp voltage for all flash chips in a SSD with a single shared external boost converter. In spacecraft and other high-radiation environments, the on-chip charge pump is the first part of the flash chip to fail, although flash memories will continue to workin read-only modeat much higher radiation levels.
 NOR flash [ edit ]In NOR flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called NOR flash because it acts like a NOR gate: when one of the word lines (connected to the cells CG) is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device. The low read latencies characteristic of NOR devices allow for both direct code execution and data storage in a single memory product. Erasing a NOR memory cell (setting it to logical 1), via quantum tunneling. Programming [ edit ]A single-level NOR flash cell in its default state is logically equivalent to a binary 1 value, because current will flow through the channel under application of an appropriate voltage to the control gate, so that the bitline voltage is pulled down.
A NOR flash cell can be programmed, or set to a binary 0 value, by the following procedure:an elevated on-voltage (typically >5 V) is applied to the CGthe channel is now turned on, so electrons can flow from the source to the drain (assuming an NMOS transistor)the source-drain current is sufficiently high to cause some high energy electrons to jump through the insulating layer onto the FG, via a process called hot-electron injection. Erasing [ edit ]To erase a NOR flash cell (resetting it to the 1 state), a large voltage of the opposite polarity is applied between the CG and source terminal, pulling the electrons off the FG through quantum tunneling. Modern NOR flash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can be performed only on a block-wise basis; all the cells in an erase segment must be erased together.
Programming of NOR cells, however, generally can be performed one byte or word at a time. NAND flash memory wiring and structure on silicon NAND flash [ edit ]NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and the bit line is pulled low only if all the word lines are pulled high (above the transistors V T). These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR flash. Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing.
Whereas NOR flash might address memory by page then word, NAND flash might address it by page, word and bit. Bit-level addressing suits bit-serial applications (such as hard disk emulation), which access only one bit at a time. Execute-in-place applications, on the other hand, require every bit in a word to be accessed simultaneously.
This requires word-level addressing. In any case, both bit and word addressing modes are possible with either NOR or NAND flash. To read data, first the desired group is selected (in the same way that a single transistor is selected from a NOR array). Next, most of the word lines are pulled up above the V T of a programmed bit, while one of them is pulled up to just over the V T of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed. Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip.
(The ground wires and bit lines are actually much wider than the lines in the diagrams.) In addition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistors. Writing and erasing [ edit ]NAND flash uses tunnel injection for writing and tunnel release for erasing. NAND flash memory forms the core of the removable USB storage devices known as USB flash drives, as well as most memory card formats and solid-state drives available today. Vertical NAND [ edit ]Vertical NAND (V-NAND) memory stacks memory cells vertically and uses a charge trap flash architecture. The vertical layers allow larger areal bit densities without requiring smaller individual cells.
 Structure [ edit ]V-NAND uses a charge trap flash geometry (pioneered in 2002 by AMD)[ citation needed] that stores charge on an embedded silicon nitride film. Such a film is more robust against point defects and can be made thicker to hold larger numbers of electrons. V-NAND wraps a planar charge trap cell into a cylindrical form.
An individual memory cell is made up of one planar polysilicon layer containing a hole filled by multiple concentric vertical cylinders. The holes polysilicon surface acts as the gate electrode. The outermost silicon dioxide cylinder acts as the gate dielectric, enclosing a silicon nitride cylinder that stores charge, in turn enclosing a silicon dioxide cylinder as the tunnel dielectric that surrounds a central rod of conducting polysilicon which acts as the conducting channel. Memory cells in different vertical layers do not interfere with each other, as the charges cannot move vertically through the silicon nitride storage medium, and the electric fields associated with the gates are closely confined within each layer.
The vertical collection is electrically identical to the serial-linked groups in which conventional NAND flash memory is configured.  Construction [ edit ]Growth of a group of V-NAND cells begins with an alternating stack of conducting (doped) polysilicon layers and insulating silicon dioxide layers. The next step is to form a cylindrical hole through these layers. In practice, a 128 Gibit V-NAND chip with 24 layers of memory cells requires about 2.9 billion such holes.
Next the holes inner surface receives multiple coatings, first silicon dioxide, then silicon nitride, then a second layer of silicon dioxide. Finally, the hole is filled with conducting (doped) polysilicon.  Performance [ edit ]As of 2013, V-NAND flash architecture allows read and write operations twice as fast as conventional NAND and can last up to 10 times as long, while consuming 50 percent less power.
They offer comparable physical bit density using 10-nm lithography, but may be able to increase bit density by up to two orders of magnitude.  Limitations [ edit ] Block erasure [ edit ]One limitation of flash memory is that, although it can be read or programmed a byte or a word at a time in a random access fashion, it can be erased only a block at a time. This generally sets all bits in the block to 1. Starting with a freshly erased block, any location within that block can be programmed. However, once a bit has been set to 0, only by erasing the entire block can it be changed back to 1. In other words, flash memory (specifically NOR flash) offers random-access read and programming operations, but does not offer arbitrary random-access rewrite or erase operations.
A location can, however, be rewritten as long as the new values 0 bits are a superset of the over-written values. For example, a nibble value may be erased to 1111, then written as 1110. Successive writes to that nibble can change it to 1010, then 0010, and finally 0000.
Essentially, erasure sets all bits to 1, and programming can only clear bits to 0. File systems designed for flash devices can make use of this capability, for example, to represent sector metadata. Although data structures in flash memory cannot be updated in completely general ways, this allows members to be removed by marking them as invalid. This technique may need to be modified for multi-level cell devices, where one memory cell holds more than one bit.
Common flash devices such as USB flash drives and memory cards provide only a block-level interface, or flash translation layer (FTL), which writes to a different cell each time to wear-level the device. This prevents incremental writing within a